Method of patterning semiconductor structure and structure thereof

ABSTRACT

Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.11/950,741, filed Dec. 5, 2007 and allowed on Mar. 23, 2011.

BACKGROUND

1. Technical Field

The disclosure relates generally to patterning of semiconductorstructure in complementary metal oxide semiconductor (CMOS) circuitsfabrication, and more particularly, to method of enhancing a patternedhard mask.

2. Background Art

In the current state of the art, continued complimentary metal oxidesemiconductor (CMOS) scaling has resulted in high density CMOScircuitry. Optical effects in the printing of patterns onto substratesof semiconductors for CMOS circuitry fabrication lead to rounding anddimensional reduction at the ends of printed lines. Often, the roundingand dimensional reduction exacerbates the effectiveness of device andcircuit operations in a densely packed circuitry. This is demonstratedin 45 nm static random access memory (SRAM) designs at the active area(RX) and polycrystalline layers.

Crystallographic etching has been recognized as a means for enhancingprinted patterns at the RX level. The use of this type of etchingtechnique requires a monocrystalline layer. However, as mostsemiconductor structures involve non-crystalline and polycrystallinelayers, the use of crystallographic etching for such enhancementpurposes cannot be applied directly to every level of semiconductorfabrication.

SUMMARY

Method of patterning a semiconductor structure is disclosed. The methodinvolves crystallographic etching techniques to enhance a patternedmonocrystalline layer as a hard mask. In one embodiment, the methodincludes bonding a monocrystalline silicon layer to a non-crystallineprotective layer; patterning the monocrystalline layer to form a hardmask; enhancing the pattern of the hard mask; stripping the hard maskafter conventional etching of protective layer; and forming a gate oxidethereon. The enhanced patterning of the hard mask is performed withcrystallographic etching to replace optical effects of rounding anddimension narrowing at the ends of a defined region with straight edgesand sharp corners. A resulting structure from the use of the enhancedpatterned hard mask includes a layer of composite materials on thesubstrate of the semiconductor structure. The layer of compositematerials includes different materials in discrete blocks defined bystraight edges within the layer.

A first aspect of the disclosure provides a method for patterning asemiconductor structure comprising: bonding a monocrystalline layer to aprotective layer disposed on the semiconductor structure;lithographically patterning the monocrystalline layer to form a hardmask; applying crystallographic etching to enhance the patterned hardmask; and etching the protective layer according to the enhancedpatterned hard mask.

A second aspect of the disclosure provides a semiconductor structurecomprising: at least one composite layer formed on a substrate, thecomposite layer including discrete blocks of different materials,wherein the discrete blocks are defined by straight edges.

A third aspect of the disclosure provides a semiconductor structurecomprising: a substrate; and multiple composite layers, wherein at leastone of the multiple composite layers is disposed on the substrate,wherein each of the multiple composite layers includes a plurality ofdiscrete blocks of different material, wherein each discrete block isdefined by straight edges.

These and other features of the present disclosure are designed to solvethe problems herein described and/or other problems not discussed.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects of the disclosure will be more readily understood fromthe following detailed description taken in conjunction with theaccompanying drawings that depict different embodiments of thedisclosure, in which:

FIGS. 1A, 2A, 3A, 4A, 5A and 6A are top views of various embodiments ofa semiconductor structure according to a method of the disclosure.

FIGS. 1B, 2B, 3B, 4B, 5B and 6B are cross-sectional views of the variousembodiments of the semiconductor structure, taken along the line A-A, incorresponding FIGS. 1A, 2A, 3A, 4A, 5A and 6A, respectively.

FIG. 7A is a top view of an embodiment of a semiconductor structureresulting from the method of FIGS. 1A-6B.

FIG. 7B is a cross-sectional view of the embodiment of the semiconductorstructure taken along the line A-A in corresponding FIG. 7A.

FIG. 8 is a cross-sectional view of an embodiment of a semiconductorstructure illustrating multiple composite layers formed by the method ofthe disclosure.

It is noted that the drawings of the disclosure are not to scale. Thedrawings are intended to depict only typical aspects of the disclosure,and therefore should not be considered as limiting the scope of thedisclosure. In the drawings, like numbering represents like elementsbetween the drawings.

DETAILED DESCRIPTION

Embodiments depicted in the drawings in FIGS. 1A-8 illustrate the methodand various resulting structures of the different aspects of fabricatinga patterned semiconductor structure 10.

FIG. 1A is a top view of a semiconductor structure 10 illustrating amonocrystalline layer 130 disposed thereon. Monocrystalline layer 130may include, for example, but not limited to: crystalline silicon (Si)of a single orientation (i.e., monocrystalline silicon). Monocrystallinelayer 130 may have a thickness ranging from approximately 10 nm toapproximately 1000 nm, and preferably within a range of approximatelyfew hundred nanometers. In FIG. 1B, monocrystalline layer 130 is bondedto a protective layer 120 using currently known or later developedprocesses. Protective layer 120 may be formed from a non-crystalline orpolycrystalline insulating material that may be suitably integrated intoa fabrication scheme. Protective layer 120 may include, for example, butis not limited to: silicon nitride, doped oxide, silicon-germanium,borosilicate glass (BSG), borophosphosilicate glass (BPSG), and anycombination thereof. Protective layer 120 is disposed on substrate 110using currently known or later developed techniques. Substrate 110 isformed, by currently known or later developed techniques, from adielectric material 112 with shallow trench isolation regions (STI) 114and pad oxide regions 116 incorporated therein. Substrate 110 mayincorporate critical threshold voltage (Vt) implants (not shown).

FIG. 2A illustrates a top view of semiconductor structure 10 where alithographic mask 140 is formed over bonded monocrystalline layer 130.FIG. 2B is a cross-sectional view of semiconductor structure 10 takenalong line A-A in FIG. 2A, showing lithographic mask 140 on bondedmonocrystalline layer 130. Lithographic etching, for example, but notlimited to, reactive ion etching (RIE), transforms bondedmonocrystalline layer 130 into hard mask 132 (FIG. 3A) having the samepattern as lithographic mask 140, which is removed concurrently.

The top view illustrated in FIG. 3A shows patterned hard mask 132 ofsingle or mono crystalline orientation over protective layer 120. FIG.3B is an alternative view showing the cross-section of semiconductorstructure 10 taken along line A-A in FIG. 3A. The pattern on hard mask132 is enhanced by currently known or later developed crystallographicetching techniques, for example, but not limited to wet etching withammonium hydroxide in a protic solvent, to form enhanced patterned hardmask 136 (FIG. 4A). The single crystalline orientation ofmonocrystalline silicon layer 130 provides for crystallographic etchingto remove any rounding and dimensional narrowing of curved surfaces 134.

As shown in FIG. 4A, enhanced patterned hard mask 136 includes straightedges 162, 164 that meet at sharp corners 138. Straight edges 162 thatare parallel keeps a substantially constant spacing; while straightedges 162 and 164 that meet are substantially perpendicular to eachother. In an alternative view illustrated in FIG. 4B, monocrystallinelayer 130, which is bonded to protective layer 120 is converted intoenhanced patterned hard mask 136 following crystallographic etching.

FIG. 5A illustrates a top view of an embodiment of semiconductorstructure 10 after further processing of protective layer 120.Protective layer 120 is etched by currently known or later developedetching techniques, for example, but not limited to, RIE, according toenhanced patterned hard mask 136 (FIG. 4A-4B). Patterned protectivelayer 120 exposes regions 118 of substrate 110, which includes portionsof STI 114 and pad oxide regions 116.

In FIG. 6A, regions 118 (FIG. 5A) are covered by an oxide layer 150deposited on substrate 110. Oxide layer 150 may include any materialsuitable for use as a gate conductor, for example, but is not limitedto, silicon dioxide (SiO₂), silicoxynitride, hafnium dioxide (HfO₂),aluminum oxide (Al₂O₃) and zirconium dioxide (ZrO₂). Oxide layer 150 isformed by currently known or later developed techniques, including forexample, but not limited to deposition and chemical mechanical polishing(CMP). Oxide layer 150 may have a thickness ranging from approximately 1nm to approximately 10 nm.

As shown in FIGS. 6A and 6B, oxide layer 150 is incorporated as part ofthe protective layer 120 covering exposed region 118 of substrate 110 toform a composite layer 170 of different materials on substrate 110.Composite layer 170 includes different materials in discrete blocks 160,defined by straight edges 162, 164 therein.

FIGS. 7A and 7B illustrate an embodiment of a resulting semiconductorstructure 10 with further processing from the structure from FIG. 6B.When remaining protective layer 120 (FIG. 6A and FIG. 6B) is strippedusing currently known or later developed processes, oxide layer 150 thatremains (FIG. 7A) presents a better defined gate conductor in discreteblock 160, defined by straight edges 200, as compared to a gateconductor created without enhanced patterned hard mask 136 (FIG. 4A-4B).

The method according to the disclosure may be repeated to form asemiconductor structure 20 (FIG. 8) with multiple composite layers 170_(i), where i=1, 2, 3, . . . n and n is an integer. FIG. 8 illustratessemiconductor structure 20 with multiple composite layers 170 _(i) builton a substrate 110. Substrate 110 may include features (not shown)including, for example, but not limited to, deep trench isolations (notshown), STI (not shown), pad oxide regions (not shown), high aspectratio via/contacts (not shown). Composite layers 170 ₁, 170 ₂, . . . 170_(n) may be interspersed with non-composite layers, for example, asingle monocrystalline layer, an oxide layer, a nitride layer, apolysilicon layer or a metal layer. Each of the composite layers 170 ₁,170 ₂, . . . 170 _(n) includes one or more discrete blocks 180 _(j), 190_(k) of different materials therein, where j and k=1, 2, 3, . . . n, andn is an integer. The thickness of each composite layer 170 _(i) may varyaccording to a desired requirement in the fabrication process. Eachdiscrete region 180 _(j) within a composite layer 170 _(i) interfaces anadjacent discrete region 190 _(k) at straight edges 200 that define thatregion. Straight edges 200 meet at specific angles according to thecrystalline characteristic of a material used in the enhanced patterningprocess of the disclosed method. For example, the specific angle may beselective to a monocrystalline material where crystallographic etchingwould result in, for example, an angle of 45°, 60° or 90° in theenhanced patterned hard mask. In the case where the specific angle is90°, the edges are perpendicular and do not taper towards each other.

The foregoing description of various aspects of the disclosure has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the scope of the invention to theprecise form disclosed, and obviously, many modifications and variationsare possible. Such modifications and variations that may be apparent toa person skilled in the art are intended to be included within the scopeof the invention as defined by the accompanying claims.

1. A semiconductor structure comprising: at least one composite layerformed on a substrate, the composite layer including discrete blocks ofdifferent materials, wherein the discrete blocks are defined by straightedges.
 2. The semiconductor structure of claim 1, wherein each of thestraight edges are substantially parallel to an adjacent straight edge.3. The semiconductor structure of claim 2, wherein each of the straightedges and an adjacent straight edge are separated at a substantiallyconstant spacing.
 4. The semiconductor structure of claim 1, whereineach of the straight edges meets an adjacent straight edge to form asubstantive right-angle.
 5. The semiconductor structure of claim 1,wherein the discrete blocks have a thickness in a range fromapproximately 1 nm to approximately 100 nm.
 6. The semiconductorstructure of claim 1, wherein each of the straight edges meets at anadjacent straight edge to form an angle selected from one of a 45°angle, a 60° angle, and a 90° angle.
 7. The semiconductor structure ofclaim 1, wherein the different materials includes one selected from agroup consisting of: a non-crystalline material, a monocrystallinematerial, a polycrystalline material and a combination thereof.
 8. Thesemiconductor structure of claim 7, wherein the different materialsinclude a gate oxide material.
 9. The semiconductor structure of claim8, wherein the gate oxide material is disposed directly above the atleast one shallow trench isolation (STI) region and the at least one padoxide region.
 10. The semiconductor structure of claim 9, wherein the atleast one shallow trench isolation (STI) region and at least one padoxide region are incorporated in the substrate.
 11. The semiconductorstructure of claim 7, wherein the different materials include oneselected from a group consisting of: silicon nitride, doped oxide,silicon-germanium, borosilicate glass (BSG), borophosphosilicate glass(BPSG), and a combination thereof.
 12. A semiconductor structurecomprising: a substrate; and multiple composite layers, wherein at leastone of the multiple composite layers is disposed on the substrate,wherein each of the multiple composite layers includes a plurality ofdiscrete blocks of different material, wherein each discrete block isdefined by straight edges.
 13. The semiconductor structure of claim 12,wherein the straight edges form an angle selective to a monocrystallinematerial used in crystallographic etching.
 14. The semiconductorstructure of claim 13, wherein the angle includes one of a 45° angle, a60° angle, and a 90° angle.
 15. The semiconductor structure of claim 12,wherein the straight edges are substantially parallel.
 16. Thesemiconductor structure of claim 12, wherein the discrete blocks have athickness in a range from approximately 1 nm to approximately 100 nm.17. The semiconductor structure of claim 12, wherein the differentmaterials include one selected from a group consisting of: siliconnitride, doped oxide, silicon-germanium, borosilicate glass (BSG),borophosphosilicate glass (BPSG), silicon dioxide (SiO₂),silicoxynitride, hafnium dioxide (HfO₂), aluminum oxide (Al₂O₃),zirconium oxide (ZrO₂), and a combination thereof.
 18. A semiconductorstructure comprising: a substrate; and multiple composite layers,wherein at least one of the multiple composite layers is disposed on thesubstrate, wherein each of the multiple composite layers includes aplurality of discrete blocks of different material, wherein eachdiscrete block is defined by substantially parallel straight edges thatform an angle selective to a monocrystalline material used incrystallographic etching.
 19. The semiconductor structure of claim 18,wherein the angle includes one of a 45° angle, a 60° angle, and a 90°angle.
 20. The semiconductor structure of claim 18, wherein the discreteblocks have a thickness in a range from approximately 1 nm toapproximately 100 nm.